1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to an integrated circuit transistor with integrated gate electrode and source/drain metallization, and to a method of making the same.
2. Description of the Related Art
A typical field effect transistor implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon layer is planarized to a desired thickness, frequently by chemical-mechanical-polishing ("CMP"), and both the polysilicon and the gate oxide are selectively etched back to the upper surface of the substrate, leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. The first implant is performed self-aligned to the gate electrode to establish lightly doped drain ("LDD") structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode by depositing and anisotropically etching a dielectric material, such as silicon dioxide. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
Early metal oxide semiconductor ("MOS") integrated circuit transistors were implemented as p-channel enhancement mode devices using aluminum as the gate electrode material. Aluminum was the material of choice due to its relatively low resistivity and material cost. Furthermore, there was already a large body of manufacturing experience with aluminum in the chip industry developed from bipolar integrated circuit processing.
A later process innovation that is still widely used today, involves the use of heavily doped polysilicon as a gate electrode material in place of aluminum. The switch to polysilicon as a gate electrode material was prompted by the recognition in the industry of certain disadvantages associated with aluminum in early fabrication technologies. In conventional semiconductor fabrication processing, aluminum must be deposited following completion of all high temperature process steps (including anneal of the source and drain regions). As a result, an aluminum gate electrode must ordinarily be separately aligned to the source and drain. This alignment procedure can adversely affect both packing density and parasitic overlap capacitances between the gate and the source/drain regions. In contrast, polysilicon with its much higher melting point, can be deposited prior to source and drain formation and therefore provide for self-aligned gate processing. Furthermore, the high temperature capability of polysilicon is routinely exploited to enable interlevel dielectric layers to be applied to provide multiple metallization layers with improved planarity.
Despite the several advantages of polysilicon over aluminum as a gate electrode material, polysilicon has the disadvantage of a much higher resistivity as compared to aluminum. Higher resistivity translates into higher values of interconnect line resistance that can lead to undesirably long RC time constants and DC voltage variations within VLSI or ULSI circuits. The development of polycide films on top of polysilicon layers has alleviated some of the resistivity shortcomings of polysilicon gate electrodes. However, the resistivity of polysilicon gate electrodes in conventional MOS integrated circuit processing still presents a potential impediment to successful process scaling through reductions in the operating voltages of VLSI and ULSI devices.
Another disadvantage of polysilicon as a gate electrode material is polysilicon depletion. In p-channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion.
In addition to the drawbacks associated with conventional gate electrode manufacture, the gate dielectric formation aspects of conventional transistor fabrication present certain disadvantages. Silicon dioxide gate oxide layers are made as thin as possible to maximize drive current and to control short channel effects. The requirement for very thin gate oxide layers has become particularly important in sub-micron processing where process scaling has dramatically increased the potential for short channel effects. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. To begin with, very thin silicon dioxide layers have been historically difficult to fabricate with a consistent thickness across a given wafer, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot-carrier-injection degradation increases. Hot carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure.
As noted above, salicidation ("self-aligned silicide formation") frequently follows source/drain formation in many conventional field effect transistor fabrication processes. The object of salicidation is to establish regions of increased conductivity over structures that are slated for interconnection with subsequently formed metallization layers. Source and drain regions and polysilicon gate electrodes are examples of such structures. The goal is to reduce the sheet resistance of the contacts to the source and drain regions and the gate electrode and to position a diffusion barrier over the silicon and polysilicon surfaces that might otherwise lead to conductor spike formation.
In a typical salicidation process, the substrate, including the gate electrode and sidewall spacers, are blanketed with a layer of silicide forming material, such as titanium. The substrate is then heated to initiate a reaction between the titanium and the silicon surfaces exposed to the titanium. These surfaces include the surfaces of the substrate on either side of the gate electrode, and the gate electrode itself, if composed of polysilicon or other silicide forming material. The reaction establishes a layer of titanium silicide over the source and drain regions and over the gate electrode, if composed of polysilicon. Any unreacted titanium is then removed by an etch process.
Metallization to the silicide is established by forming a dielectric layer over the silicide and opening contact holes in the dielectric layer down to the silicide layer by etching. A conducting material, frequently a metal, is then deposited over the dielectric layer and into the contact holes. The portion of the metal layer positioned above the holes is planarized, frequently by CMP.
One difficulty with the aforementioned conventional processes is the sheer number of separate process steps involved. For example, gate formation, silicide formation and silicide-metallization require at least two separate planarization steps, one for the gate deposition and one for the silicide-metallization deposition, and two to three conductor deposition steps, one each for the gate, the silicide and the silicide-metallization. Furthermore, where endpoint detection is less than optimal, the etch of the dielectric layer to form contact holes may damage the silicide layer, resulting in poor device performance.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.